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4052

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The Tektronix 4052 is a graphics-capable desktop microcomputer produced by Tektronix in the late 1970s through the early 1980s. The display technology is similar to the Tektronix 4010 terminal, using a vector-driven direct-view storage CRT display (like an analog storage scope) to avoid the need for video RAM. The 4052 is an all-in-one design, with the display, keyboard, CPU and DC300 quarter-inch cartridge tape drive in a single desktop case, and includes a GPIB interface. A simple operating system and BASIC interpreter is included in ROM.

The storage tube display allows the screen to retain images drawn to it, eliminating the need for frame-buffer memory. This allows the resolution to be as high as the hardware can handle, which is 1024 by 1024 logically (i.e. DAC resolution) but limited by the physical layout of the screen to 1024 by 780. It also allows the machine to dedicate all of its memory to the programs running on it (as opposed to partitioning off a section for the buffer), an important consideration at the time when memory was expensive and scarce.

Released in 1978, the 4952 came with a full 32 kB of RAM for $9,795 (2016 value: $36,300) and could be expanded to 64 kB for another $1,995 (2016: $7,400).

The 4054 is a version of the 4052 built around the 19" screen from the 4014 terminal rather than the 11" screen from the 4012, increasing display resolution to 4,096 by 3,072. The 4054 also had an option to display a limited amount of refreshed graphics that used a Signetics 8X300, an early RISC-like microprocessor.

Architecture

Unlike the 4051, which is based on an 8-bit Motorola 6800 CPU, the 4052 CPU is based on four AMD 2901 4-bit bit-slice processors used together to make a single 16-bit processor. The processor is microcoded to emulate a 6800 so it can run the 4051 firmware, written in 6800 assembler, with minimal changes. The original goal of the project was to run 8 times faster than the 4051. This was to be achieved by three "factors of 2": First, the processor clock is 2 MHz, compared to the 1 MHz of the 4051 (the 2 MHz was set by the speed of the EPROMs initially used to hold the microcode). Second, the memory is 16 bits wide instead of 8, so two bytes can be accessed in a cycle, theoretically doubling the memory access speed. Finally, the data and code address spaces are separate (Harvard architecture) so program fetch of the next instruction can in principle be overlapped with processing data from the previous instruction.

However, the 4051 firmware was written for the 8-bit 6800 processor so the 16-bit memory access is rarely of any benefit. The overlapping of instruction and data fetch was complicated to implement and was abandoned for the first version of the product. The result was a system with between 2 and 3 times the performance of the 4051. Early in the project, it was proposed that the 6800-assembler-coded implementation of 48-bit floating-point arithmetic used in the 4051 firmware be implemented in microcode, but Tek management vetoed the idea until it became obvious that the performance goals would not be met without it. So, late in the project, the floating-point operations were implemented in microcode by adding new opcodes in gaps in the 6800 opcode map, and the firmware was rewritten to use the new opcodes instead of calling the floating-point subroutines. The result was about a 30-times improvement in speed over the 4051. This was because graphics operations are floating-point intensive − every move or draw requires two multiplies and two adds to convert from the user's coordinate space to screen coordinates. Also other numeric-intensive operations such as matrix calculations benefited.

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