Difference between revisions of "4052"

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==Architecture ==
 
==Architecture ==
Unlike the [[4051]], which was based on an 8-bit Motorola 6800 CPU, the 4052 had a CPU based on four [http://en.wikipedia.org/wiki/AMD_Am2900 AMD 2901 4-bit bit-slice processors] used together to make a single 16-bit processor. The processor was microcoded to emulate a 6800 so it could run the 4051 firmware, written in 6800 assembler, with minimal changes. The original goal of the project was to run 8 times faster than the 4051. This was to be achieved by three "factors of 2": First, the processor ran at 2 Mhz, compared to the 1 MHz of the 4051 (the 2 MHz was set by the speed of the EPROMs initially used to hold the microcode). Second, the memory was 16 bits wide instead of 8, so two bytes could be accessed in a cycle, theoretically doubling the memory access speed. Finally, the data and code address spaces were separate (Harvard architecture) so program fetch of the next instruction could be overlapped with processing data from the previous instruction. However, the 4051 firmware was written for the 8-bit 6800 processor so the 16-bit memory access was rarely of any benefit. The overlapping of instruction and data fetch was complicated, and was abandoned for the first version of the product. The result was a system with between 2 and 3 times the performance of the 4051. Early in the project, it was proposed that the 6800-assembler-coded implementation of 48-bit floating-point arithmetic used in the 4051 firmware be implemented in microcode, but the management vetoed the idea until it became obvious that the performance goals would not be met without it. So, late in the project, the floating-point operations were implemented in microcode by adding new opcodes in gaps in the 6800 opcode map and the firmware was rewritten to use the new opcodes instead of calling the floating-point subroutines. The result was about a 30-times improvement in speed over the 4051. This was because graphics operations are floating-point intensive -- every move or draw requires two multiplies and two adds to convert from the user's coordinate space to screen coordinates. Also other numeric-intensive operations such as matrix calculations benefited.
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Unlike the [[4051]], which was based on an 8-bit Motorola 6800 CPU, the 4052 had a CPU based on four [http://en.wikipedia.org/wiki/AMD_Am2900 AMD 2901 4-bit bit-slice processors] used together to make a single 16-bit processor. The processor was microcoded to emulate a 6800 so it could run the 4051 firmware, written in 6800 assembler, with minimal changes. The original goal of the project was to run 8 times faster than the 4051. This was to be achieved by three "factors of 2": First, the processor ran at 2 MHz, compared to the 1 MHz of the 4051 (the 2 MHz was set by the speed of the EPROMs initially used to hold the microcode). Second, the memory was 16 bits wide instead of 8, so two bytes could be accessed in a cycle, theoretically doubling the memory access speed. Finally, the data and code address spaces were separate (Harvard architecture) so program fetch of the next instruction could be overlapped with processing data from the previous instruction.  
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However, the 4051 firmware was written for the 8-bit 6800 processor so the 16-bit memory access was rarely of any benefit. The overlapping of instruction and data fetch was complicated, and was abandoned for the first version of the product. The result was a system with between 2 and 3 times the performance of the 4051. Early in the project, it was proposed that the 6800-assembler-coded implementation of 48-bit floating-point arithmetic used in the 4051 firmware be implemented in microcode, but the management vetoed the idea until it became obvious that the performance goals would not be met without it. So, late in the project, the floating-point operations were implemented in microcode by adding new opcodes in gaps in the 6800 opcode map and the firmware was rewritten to use the new opcodes instead of calling the floating-point subroutines. The result was about a 30-times improvement in speed over the 4051. This was because graphics operations are floating-point intensive every move or draw requires two multiplies and two adds to convert from the user's coordinate space to screen coordinates. Also other numeric-intensive operations such as matrix calculations benefited.
  
 
==Links==
 
==Links==

Revision as of 06:48, 4 May 2018

4052.jpg

The Tektronix 4052 was a graphics-capable desktop microcomputer produced by Tektronix in the late 1970s through the early 1980s. The display technology was similar to the Tektronix 4010 terminal, using a vector-driven direct-view storage tube display (like an analog storage scope) to avoid the need for video RAM. It was all-in-one designs with the display, keyboard, CPU and DC300 quarter-inch cartridge tape drive in a single desktop case, and included a GPIB interface. A simple operating system and BASIC interpreter were included in ROM.

The storage tube display allowed the screen to retain images drawn to it, eliminating the need for frame-buffer memory. This allowed the resolution to be as high as the hardware could handle, which was ostensibly 1024 by 1024 but limited by the physical layout of the screen to 1024 by 780. It also allowed the machine to dedicate all of its memory to the programs running on it, as opposed to partitioning off a section for the buffer.

Released in 1978, the 4952 came with a full 32 kB of RAM for $9,795 (2016 value: $36,300) and could be expanded to 64 kB for another $1,995 (2016: $7,400).

The 4054 was a version of the 4052 built around the 19" screen from the 4014 terminal rather than the 11" screen from the 4012, increasing resolution to 4,096 by 3,072. The 4054 also had an option to display a limited amount of refreshed graphics that used a Signetix 8X300, an early RISC processor.

Architecture

Unlike the 4051, which was based on an 8-bit Motorola 6800 CPU, the 4052 had a CPU based on four AMD 2901 4-bit bit-slice processors used together to make a single 16-bit processor. The processor was microcoded to emulate a 6800 so it could run the 4051 firmware, written in 6800 assembler, with minimal changes. The original goal of the project was to run 8 times faster than the 4051. This was to be achieved by three "factors of 2": First, the processor ran at 2 MHz, compared to the 1 MHz of the 4051 (the 2 MHz was set by the speed of the EPROMs initially used to hold the microcode). Second, the memory was 16 bits wide instead of 8, so two bytes could be accessed in a cycle, theoretically doubling the memory access speed. Finally, the data and code address spaces were separate (Harvard architecture) so program fetch of the next instruction could be overlapped with processing data from the previous instruction.

However, the 4051 firmware was written for the 8-bit 6800 processor so the 16-bit memory access was rarely of any benefit. The overlapping of instruction and data fetch was complicated, and was abandoned for the first version of the product. The result was a system with between 2 and 3 times the performance of the 4051. Early in the project, it was proposed that the 6800-assembler-coded implementation of 48-bit floating-point arithmetic used in the 4051 firmware be implemented in microcode, but the management vetoed the idea until it became obvious that the performance goals would not be met without it. So, late in the project, the floating-point operations were implemented in microcode by adding new opcodes in gaps in the 6800 opcode map and the firmware was rewritten to use the new opcodes instead of calling the floating-point subroutines. The result was about a 30-times improvement in speed over the 4051. This was because graphics operations are floating-point intensive − every move or draw requires two multiplies and two adds to convert from the user's coordinate space to screen coordinates. Also other numeric-intensive operations such as matrix calculations benefited.

Links